with HP16550A style triggers -
Download Latest Release
Source Code Respoitory
I ported the OLS FPGA into Verilog (with which I'm more
familiar). I then started on a quest to pack as much in as
possible. After all, if one has an FPGA image
downloader (see above), one needs an image to download. :-)
How much of a big HP 16500/16550 timing logic analyzer can
MOST of it. Really!
I've written a full spec for
it, but in addition "testbench_adv.v" in the
download shows the
various options. The heavy lifter is in
"trigger_adv.v". My next big project is writing a client
app to program the
triggers. In the meantime, I hope you like it!
For latest news, please read the discussion
forum at Dangerous Prototypes.
-- ols_verilog_release7.zip (246k) -- Verilog
Source, Xilinx ISE stuff, BIT & MCS files --
-- Select "logic_sniffer.bit" within XISE folder using my FPGA Image Loader --
format (1.1MBytes) --
-- PDF format (673k) --
HP16550a Style Trigger Terms:
- 10 more 32-bit masked value comparisons.
- 2 range checks.
- 2 edge checks (rising, falling, both, neither).
- 2 36-bit timers (10ns to 600sec range).
HP16550a Style States:
- 16 state FSM
- Each state can use any combination
(AND/NAND/OR/NOR/XOR/NXOR) of the trigger terms
for detecting a "hit" condition, and "else" condition, or "capture"
- The "hit" condition actions include setting
trigger(run), starting/stopping timers, and advancing to the next
state. The hit condition also has a 20-bit "occurrence"
counter. The hit condition must occur 'x' number of times before
the hit actions are taken.
- The "else" condition lets you jump to another
- If neither hit or else condition matches, the state
- The "capture" condition controls what gets sampled
into RAM (prior to asserting the trigger).
|Grab the 16550a user's guide (Google for
"HP 16550a" - it's the first
hit). I think you'll be surprised how much got squeezed in.
The previous Logic Sniffer legacy/basic triggers are also still
there. The advanced trigger & legacy triggers can be
used in parallel, though you lose the advanced trigger conditional
"capture". Arming basic triggers immediately starts filling the
The FPGA is
compiled using Xilinx's ISE Design Suite
Webpack. It's large & takes a while to download &
install. You'll also be prompted to get a Webpack license -
just a few clicks on a webpage
the the installer send you to. You can download it from
I use a low-level FPGA primitive called a
LUT-RAM for most of this
stuff. An fpga is large array of LUT's with a flop (optional)
attached. LUT's are 16-bit RAM's, and serially configured during
bootstrap to describe
combinatorial logic. Think shift-register.
However... you can dynamically change the contents of LUT
RAM's. Thus a single LUT can evaluate 4 bits of indata directly.
I use them for the trigger terms, range checks -- in combination with a
fast-carry-chain primitive -- and edge checks. I also use
them for combining the results of the trigger terms.
Nothing is entirely free, and configuring this thing is...
involved. There is over 11000 config
bits. I've defined two long commands, for selecting config
addresses (0x9E) & writing data to the trigger (0x9F). These
pump data serially into the LUT RAM's.
As proof of concept, I revamped the legacy/basic triggers to use the
same LUT based logic. It remains fully client compatible,
assuming said client writes the data & masks for each trigger
Open "ols-verilog.xise" within XISE folder using in Xilinx ISE.
Click on "Generate
Programming File", and it should finish within a few minutes
Install the compiled image "logic_sniffer.bit" on your OLS using my FPGA Image Loader.
I use the free Icarus-Verilog to simulate it.
Offical site: http://www.icarus.com/eda/verilog
Wiki Documentation: http://iverilog.wikia.com
Download Windows version here: http://bleyer.org/icarus
I've provided scripts (batch files) in the OLS release to
launch simulations & view results in the GTK waveform viewer
(included with the Windows release).
- Release 1 - January 26th, 2011 - Initial Release
- Release 2 - Fixed SPI issue fouling up the Query ID.
- Release 3 - Fixed problem talking to PIC firmware
- Release 4 - Fixed Xilinx XISE to use correct speed
grade. RLE now works!
- Release 5 - Restored meta data, minor fixes to ensure
ram writes what adv-trigger wants captured, & misc logic resets to
known state. Documented the extra RLE-modes. Also, the verilog port is
now on official Gadget Factory SVN!
- Release 6 - Removed inclusive-RLE mode, since breaks
older clients and is no longer used by Jawi's. Please
be sure to use at least version 0.9.3 of Jawi's